A 3D reconstruction from real-time stereoscopic images using GPU

IEEE Xplore Compliant Files 979-10-92279-01-6International audienceIn this article we propose a new technique to obtain a three-dimensional (3D) reconstruction from stereoscopic images taken by a stereoscopic system in real-time. To parallelize the 3D reconstruction we propose a method that uses a Graphics Processors Unit (GPU) and a disparity map from block matching algorithm (BM). The results obtained permit us to accelerate the images processing time, measured in frames per second (FPS) with respect to the same method using a Central Processing Unit (CPU). The advantage of speed using GPU advocates our system for practical applications such as aerial reconnaissance, cartography, robotic navigation and obstacle detection

SignalPU: A programming model for DSP applications on parallel and heterogeneous clusters

International audience—The biomedical imagery, the numeric communi-cations, the acoustic signal processing and many others digital signal processing applications (DSP) are present more and more everyday in the numeric world. They process growing data volume which is represented with more and more accuracy, and using complex algorithms with time constraints to satisfying. Con-sequently, a high requirement of computing power characterize them. To satisfy this need, it's inevitable today to use parallel and heterogeneous architectures in order to speed-up the processing, where the best examples are the supercomputers like "Tianhe-2" and "Titan" of the ranking top500. These architectures with their multi-core nodes supported by many-core accelerators offer a good response to this problem, but they are still hard to program in order to make performance because of lot of things like synchronization, the memory management, the hardware specifications . . . In the present work, we propose a high level programming model to implement easily and efficiently digital signal processing applications on heterogeneous clusters

Systematic Figure of Merit Computation for the Design of Pipeline ADC

Submitted on behalf of EDAA (http://www.edaa.com/)International audienceThe emerging concept of SoC-AMS leads to research new top-down methodologies to aid systems designers in sizing analog and mixed devices. This work applies this idea to the high-level optimization of pipeline ADC. Considering a given technology, it consists in comparing different configurations according to their imperfections and their architectures without FFT computation or time-consuming simulations. The final selection is based on a figure of merit

Outils d'aide à la conception de systèmes mixtes analogiques/numériques dédiés à la radio logicielle

L'émergence de la radio logicielle restreinte (Software Defined Radio - SDR) conduit à développer de nouvelles méthodologies de conception et de prototypage rapide de systèmes de télécommunications mixtes (analogiques/numériques) tout en imposant la reconfigurabilité et la généricité des solutions proposées. Cette étude consiste en une exploration architecturale focalisée sur deux thèmes principaux : la conversion analogique numérique (CAN) et les traitements numériques haute fréquence associés (Front-End Numérique ou FEN) pour un récepteur mobile. Le concept SoC-AMS conduit à rechercher des méthodologies de conception descendantes semblables à la conception numérique et appliquées au monde analogique et mixtes. L'application se tourne vers l'optimisation haut niveau des CAN pipeline et se base sur l'utilisation d'une fonction de mérite. La construction du FEN s'appuie sur un découpage modulaire original des différentes fonctions synthétisables en VHDL (filtrage, conversion de fréquences d'échantillonnage). Un outil de synthèse spécifique complète cette étude et permet de faire le lien entre les spécifications et l'implémentation sur une plateforme de prototypage mixte comprenant un FPGA et deux CAN pipeline. L'ensemble CAN / FEN constitue le Front-End Mixte (FEM). Le langage VHDL-AMS utilisé pour la modélisation comportementale haut niveau de systèmes mixtes permet de valider le FEM dans son ensemble

Design methodology for runtime reconfigurable FPGA: From high level specification down to implementation

In this paper we present an automatic design generation methodology for heterogeneous architectures composed of processors, DSPs and FPGAs. This methodology is based on an Adequation Algorithm Architecture where application is represented by a control data flow graph and architecture by an architecture graph. We focus on how to take into account specificities of partially reconfigurable components during the adequation process and for the design generation. We present a method which generates automatically the design for both fixed and partially reconfigurable parts of a FPGA. This method uses prefetching technic to minimize reconfiguration latency of runtime reconfiguration and buffer merging to minimize memory requirements of the generated design

Outils d'aide à la conception de systèmes mixtes analogiques/numériques dédiés à la radio logicielle

L'émergence de la radio logicielle restreinte (Software Defined Radio - SDR) conduit à développer de nouvelles méthodologies de conception et de prototypage rapide de systèmes de télécommunications mixtes (analogiques/numériques) tout en imposant la reconfigurabilité et la généricité des solutions proposées. Cette étude consiste en une exploration architecturale focalisée sur deux thèmes principaux : la conversion analogique numérique (CAN) et les traitements numériques haute fréquence associés (Front-End Numérique ou FEN) pour un récepteur mobile. Le concept SoC-AMS conduit à rechercher des méthodologies de conception descendantes semblables à la conception numérique et appliquées au monde analogique et mixtes. L'application se tourne vers l'optimisation haut niveau des CAN pipeline et se base sur l'utilisation d'une fonction de mérite. La construction du FEN s'appuie sur un découpage modulaire original des différentes fonctions synthétisables en VHDL (filtrage, conversion de fréquences d'échantillonnage). Un outil de synthèse spécifique complète cette étude et permet de faire le lien entre les spécifications et l'implémentation sur une plateforme de prototypage mixte comprenant un FPGA et deux CAN pipeline. L'ensemble CAN / FEN constitue le Front-End Mixte (FEM). Le langage VHDL-AMS utilisé pour la modélisation comportementale haut niveau de systèmes mixtes permet de valider le FEM dans son ensemble

Influence of number, location and size of faces on gaze in video

Many studies have reported the preference for faces and influence of faces on gaze, most of them in static images and a few in videos. In this paper, we study the influence of faces in complex free-viewing videos, with respect to the effects of number, location and size of the faces. This knowledge could be used to enrich a face pathway in a visual saliency model. We used eye fixation data from an eye movement experiment, hand-labeled all the faces in the videos watched, and compared the labeled face regions against the eye fixations. We observed that fixations made are in proximity to, or inside the face regions. We found that 50% of the fixations landed directly on face regions that occupy less than 10% of the entire visual scene. Moreover, the fixation duration on videos with face is longer than without face, and longer than fixation duration on static images with faces. Finally, we analyzed the three influencing factors (Eccentricity, Area, Closeness) with linear regression models. For one face, the E +A combined model is slightly better than the E model and better than the A model. For two faces, the three variables (E,A,C) are tightly coupled and the E +A+C model had the highest score.

Speed-up run-time reconfiguration implementation on FPGAs

International audienceReconfigurable computing is certainly one of the most important emerging research topics over the last few years, in the field of digital processing architectures. The introduction of run-time reconfiguration (RTR) on FPGAs requires appropriate design flows and methodologies to fully exploit this new functionality. For that purpose we present an automatic design generation methodology for heterogeneous architectures based on Network on Chip (NoC) and FPGAs that eases and speed-up RTR implementation. We focus on how to take into account specificities of partially reconfigurable components during the design generation steps. This method automatically generates designs for both fixed and partially reconfigurable parts of a FPGA with automaticmanagement of the reconfiguration process. Furthermore this automatic design generation enables reconfiguration pre-fetching techniques to minimize reconfiguration latency and buffer merging techniques to minimize memory requirements of the generated design. This concept has been applied to different wireless access schemes, based on a combination of OFDM and CDMA techniques. The implementation example illustrates the benefits of the proposed design methodology

Adaptive Mesh Reconstruction in X-Ray Tomography

International audiencehis paper presents an X-ray tomographic reconstruction method based on an adaptive mesh in order to directly obtain the typical gray level reconstructed image simultaneously with its segmentation. It also leads to reduce the number of unknows throughout the iterations of reconstruction and accelerates the process of algebraic algorithms. The process of reconstruction is no more based on a regular grid of voxels but on a mesh composed of non regular tetraedra that are progressively adapted to the content of the image. Each iteration is composed by two main steps that successively estimate the values of the mesh elements and segment the sample in order to make the grid adapted to the content of the image. The method was applied on numerical and experimental data. The results show that the method provides reliable reconstructions and leads to drastically reduce the memory storage compared to usual reconstructions based on pixel representation

Tetrahedral Volume Reconstruction in X-Ray Tomography using GPU Architecture

International audienceIn this paper, we propose the use of the graphics processor unit (GPU) to accelerate a ray-tracing method in the framework of X-ray tomographic image reconstruction. We first describe an innovative iterative reconstruction method we have developed based on a tetrahedral volume with conjugate gradient. We do not use voxels here but instead tetrahedrons to increase the quality of reconstruction and the reduction of data as thus we need less resolution of the volume to fit the object reconstructed. This is an important point to use the GPU. We present here the algorithms adapted to the GPU and the results obtained compared to CPU